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Please use this identifier to cite or link to this item: https://dspace.lboro.ac.uk/2134/20534

Title: An efficient multiple precision floating-point Multiply-Add Fused unit
Authors: Manolopoulos, K.
Reisis, D.
Chouliaras, V.A.
Keywords: Floating-point
Multiply-Add Fused
Multiple precision
Issue Date: 2016
Publisher: © Elsevier
Citation: MANOLOPOULOS, K., REISIS, D. and CHOULIARAS, V.A., 2016. An efficient multiple precision floating-point Multiply-Add Fused unit. Microelectronics Journal, 49, pp. 10 - 18
Abstract: Multiply-Add Fused (MAF) units play a key role in the processor's performance for a variety of applications. The objective of this paper is to present a multi-functional, multiple precision floating-point Multiply-Add Fused (MAF) unit. The proposed MAF is reconfigurable and able to execute a quadruple precision MAF instruction, or two double precision instructions, or four single precision instructions in parallel. The MAF architecture features a dual-path organization reducing the latency of the floating-point add (FADD) instruction and utilizes the minimum number of operating components to keep the area low. The proposed MAF design was implemented on a 65 nm silicon process achieving a maximum operating frequency of 293.5 MHz at 381 mW power.
Description: This paper was accepted for publication in the journal Microelectronics Journal and the definitive published version is available at http://dx.doi.org/10.1016/j.mejo.2015.10.012.
Version: Accepted for publication
DOI: 10.1016/j.mejo.2015.10.012
URI: https://dspace.lboro.ac.uk/2134/20534
Publisher Link: http://dx.doi.org/10.1016/j.mejo.2015.10.012
ISSN: 0026-2692
Appears in Collections:Published Articles (Mechanical, Electrical and Manufacturing Engineering)

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