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Please use this identifier to cite or link to this item: https://dspace.lboro.ac.uk/2134/21295

Title: BioThreads: a novel VLIW-based chip multiprocessor for accelerating biomedical image processing applications
Authors: Stevens, David
Chouliaras, V.A.
Azorin-Peris, Vicente
Zheng, Jia
Echiadis, Angelos S.
Hu, Sijung
Keywords: Biomedical image processing
Field programmable gate arrays (FPGAs)
Imaging photoplethysmography (IPPG)
Multicore processing
Issue Date: 2011
Publisher: © IEEE
Citation: STEVENS, D. ... et al., 2011. BioThreads: a novel VLIW-based chip multiprocessor for accelerating biomedical image processing applications. IEEE Transactions on Biomedical Circuits and Systems, DOI: 10.1109/TBCAS.2011.2166962.
Abstract: We discuss BioThreads, a novel, configurable, extensible system-on-chip multiprocessor and its use in accelerating biomedical signal processing applications such as imaging photoplethysmography (IPPG). BioThreads is derived from the LE1 open-source VLIW chip multiprocessor and efficiently handles instruction, data and thread-level parallelism. In addition, it supports a novel mechanism for the dynamic creation, and allocation of software threads to uncommitted processor cores by implementing key POSIX Threads primitives directly in hardware, as custom instructions. In this study, the BioThreads core is used to accelerate the calculation of the oxygen saturation map of living tissue in an experimental setup consisting of a high speed image acquisition system, connected to an FPGA board and to a host system. Results demonstrate near-linear acceleration of the core kernels of the target blood perfusion assessment with increasing number of hardware threads. The BioThreads processor was implemented on both standard-cell and FPGA technologies; in the first case and for an issue width of two, full real-time performance is achieved with 4 cores whereas on a mid-range Xilinx Virtex6 device this is achieved with 10 dual-issue cores. An 8-core LE1 VLIW FPGA prototype of the system achieved 240 times faster execution time than the scalar Microblaze processor demonstrating the scalability of the proposed solution to a state-of-the-art FPGA vendor provided soft CPU core.
Description: © 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
Version: Accepted for publication
DOI: 10.1109/TBCAS.2011.2166962
URI: https://dspace.lboro.ac.uk/2134/21295
Publisher Link: http://dx.doi.org/10.1109/TBCAS.2011.2166962
ISSN: 1932-4545
Appears in Collections:Published Articles (Mechanical, Electrical and Manufacturing Engineering)

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