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Title: VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads
Authors: Chouliaras, V.A.
Stevens, David
Dwyer, Vincent M.
Keywords: RTL implementation
Embedded microprocessors
Hardware/software interface
Configurable VLIW architectures
Field-programmable gate array design
Standard-cell design
Issue Date: 2016
Publisher: © Elsevier
Citation: CHOULIARAS, V.A., STEVENS, D. and DWYER, V.M., 2016. VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads. Microprocessors and Microsystems, In Press.
Abstract: We discuss VThreads, a novel VLIW CMP with hardware-assisted shared-memory Thread support. VThreads supports Instruction Level Parallelism via static multiple-issue and Thread Level Parallelism via hardware-assisted POSIX Threads along with extensive customization. It allows the instantiation of tightlycoupled streaming accelerators and supports up to 7-address Multiple-Input, Multiple-Output instruction extensions. VThreads is designed in technology-independent Register-Transfer-Level VHDL and prototyped on 40 nm and 28 nm Field-Programmable gate arrays. It was evaluated against a PThreads-based multiprocessor based on the Sparc-V8 ISA. On a 65 nm ASIC implementation VThreads achieves up to x7.2 performance increase on synthetic benchmarks, x5 on a parallel Mandelbrot implementation, 66% better on a threaded JPEG implementation, 79% better on an edge-detection benchmark and ~13% improvement on DES compared to the Leon3MP CMP. In the range of 2 to 8 cores VThreads demonstrates a post-route (statistical) power reduction between 65% to 57% at an area increase of 1.2%-10% for 1-8 cores, compared to a similarly-configured Leon3MP CMP. This combination of micro-architectural features, scalability, extensibility, hardware support for low-latency PThreads, power efficiency and area make the processor an attractive proposition for low-power, deeply-embedded applications requiring minimum OS support.
Description: This paper is in closed access until 12th July 2017.
Sponsor: This research was partially supported by the EU FP7 ENOSYS project
Version: Accepted for publication
DOI: 10.1016/j.micpro.2016.07.010
URI: https://dspace.lboro.ac.uk/2134/22091
Publisher Link: http://dx.doi.org/10.1016/j.micpro.2016.07.010
ISSN: 0141-9331
Appears in Collections:Closed Access (Mechanical, Electrical and Manufacturing Engineering)

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