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Please use this identifier to cite or link to this item: https://dspace.lboro.ac.uk/2134/22466

Title: Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: a case study in telephony workloads
Authors: Chouliaras, V.A.
Koutsomyti, Konstantia
Parr, Simon
Mulvaney, David J.
Milward, Mark
Keywords: VLSI
Vector processors
System-on-Chip (SoC)
Electronic System Level (ESL) design
Issue Date: 2013
Publisher: © Elsevier
Citation: CHOULIARAS, V. ... et al., 2013. Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: a case study in telephony workloads. Microprocessors and Microsystems, 37 (8D), pp.1122-1143.
Abstract: This research discusses hardware architectures, script-based automation and software and hardware methodologies for developing customized System-on-Chip scalar/vector processors within the example application domain of telephony codes. The approaches researched include Register-Transfer-Level methodologies resulting in an SIMD-enhanced processor known as the ITU-VE1, and Electronic System Level methodologies resulting in a multi-parallel vector processor known as the SS-SPARC. The example applications were the ITU-T G.729A and G.723.1 speech codecs chosen for their abundant data-level parallelism and availability for research purposes. Results indicate the proposed scalar/vector accelerators achieve a maximum speed-up of 4.27 and 4.62 for the G729.A and G723.1 encoders respectively for 512-bit wide SIMD configurations. Both vector processors resulting from the proposed methodologies were implemented as VLSI macros and compared at the silicon level. Compared to the Register-Transfer-Level flow, the Electronic System Level flow implementing the same datapath results in increased power consumption of 3-15% however delivers an area reduction of 2-18% and substantially shortens design and verification time making it a viable alternative to established RTL methodologies.
Description: Closed access.
Sponsor: This research was supported by EPSRC Grant GR/S44976/01.
Version: Published
DOI: 10.1016/j.micpro.2013.10.001
URI: https://dspace.lboro.ac.uk/2134/22466
Publisher Link: http://dx.doi.org/10.1016/j.micpro.2013.10.001
ISSN: 0141-9331
Appears in Collections:Closed Access (Mechanical, Electrical and Manufacturing Engineering)

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