Software and hardware techniques for accelerating MPEG2 motion estimation

The aim of this thesis is to accelerate the process of motion estimation (ME) for the implementation of real time, portable video encoding. To this end a number of different techniques have been considered and these have been investigated in detail. Data Level Parallelism (DLP) is exploited first, through the use of vector instruction extensions using configurable/re-configurable processors to form a fast System-On-Chip (SoC) video encoder capable of embedding both full search and fast ME methods. Further parallelism is then exploited in the form of Thread Level Parallelism (TLP), introduced into the ME process through the use of multiple processors incorporated onto a single Soc. A theoretical explanation of the results, obtained with these methodologies, is then developed for algorithmic optimisations. This is followed with the investigation of an efficient, orthogonal technique based on the use of a reduced number of bits (RBSAD) for the purposes of image comparison. This technique, which provides savings of both power and time, is investigated along with a number of criteria for its improvement to full resolution. Finally a VLSI layout of a low-power ME engine, capable of using this technique, is presented. The combination of DLP, TLP and RBSAD is found to reduce the clock frequency requirement by around an order of magnitude.