+44 (0)1509 263171
Please use this identifier to cite or link to this item:
|Title: ||Complex low volume electronics simulation tool to improve yield and reliability|
|Authors: ||Segura-Velandia, Diana M.|
Conway, Paul P.
West, Andrew A.
Whalley, David C.
Wilson, Antony R.
Huertas-Quintero, Lina A.M.
|Issue Date: ||2007|
|Publisher: ||© IEEE|
|Citation: ||SEGURA-VELANDIA, D.M. ... et al, 2007. Complex low volume electronics simulation tool to improve yield and reliability. IN: Proceedings, 32nd IEEE Electronic Manufacturing Technology Symposium, IEMT '07. San Jose, CA, USA, 3-5 Oct. 2007, pp. 1 - 7|
|Abstract: ||Assembly of Printed Circuit Boards (PCB) in low volumes
and a high-mix requires a level of manual intervention during
product manufacture, which leads to poor first time yield and
increased production costs. Failures at the component-level
and failures that stem from non-component causes (i.e.
system-level), such as defects in design and manufacturing,
can account for this poor yield. These factors have not been
incorporated in prediction models due to the fact that systemfailure
causes are not driven by well-characterised
deterministic processes. A simulation and analysis support
tool being developed that is based on a suite of interacting
modular components with well defined functionalities and
interfaces is presented in this paper. The CLOVES (Complex
Low Volume Electronics Simulation) tool enables the
characterisation and dynamic simulation of complete design;
manufacturing and business processes (throughout the entire
product life cycle) in terms of their propensity to create
defects that could cause product failure. Details of this system
and how it is being developed to fulfill changing business
needs is presented in this paper. Using historical data and
knowledge of previous printed circuit assemblies (PCA)
design specifications and manufacturing experiences, defect
and yield results can be effectively stored and re-applied for
future problem solving. For example, past PCA design
specifications can be used at design stage to amend designs or
define process options to optimise the product yield and
|Description: ||This is a conference paper [© IEEE]. It is also available from: http://ieeexplore.ieee.org/servlet/opac?punumber=4417035. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Appears in Collections:||Conference Papers and Contributions (Mechanical, Electrical and Manufacturing Engineering)|
Files associated with this item:
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.