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Title: A system-on-chip vector multiprocessor for transmission line modelling acceleration
Authors: Chouliaras, V.A.
Flint, James A.
Li, Y.
Nunez-Yanez, Jose L.
Issue Date: 2005
Publisher: © IEEE
Citation: CHOULIARAS, V.A. ... et al., 2005. A system-on-chip vector multiprocessor for transmission line modelling acceleration. IN: IEEE Workshop on Signal Processing Systems Design and Implementation (SiPS 2005), Athens, Greece, 2-4 November, pp. 568-572.
Abstract: We discuss a configurable, System-on-Chip vector multiprocessor for accelerating the Transmission Line Modeling (TLM) algorithm with an architecture capable of exploiting the two primary forms of parallelism in the code, thread and data level parallelism. Theoretical results demonstrate an order of magnitude reduction in the dynamic instruction count for a scalar-processor/vector-coprocessor configuration at a vector length of sixteen 32-bit singleprecision elements. Furthermore, a multi-vector SoC architecture consisting of ten such vector accelerators provides a near-linear theoretical performance benefit of the order of 88% in three out of four benchmark configurations which is orthogonal to the benefit realized by vectorization alone. We discuss in detail this potent architecture and present implementation data for the 2-way multi-processor VLSI macrocell.
Description: This is a conference paper [© IEEE]. It is also available at: http://ieeexplore.ieee.org/ Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Version: Published
DOI: 10.1109/SIPS.2005.1579931
URI: https://dspace.lboro.ac.uk/2134/6162
ISBN: 0780393333
ISSN: 1520-6130
Appears in Collections:Conference Papers and Contributions (Electronic, Electrical and Systems Engineering)

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