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Title: Parametric data-parallel architectures for TLM acceleration
Authors: Chouliaras, V.A.
Flint, James A.
Li, Y.
Issue Date: 2004
Publisher: © IEEE
Citation: CHOULIARAS, V.A., FLINT, J.A. and LI, Y., 2004. Parametric data-parallel architectures for TLM acceleration. IN: Proceedings of 3rd International Conference on Computational Electromagnetics and Its Applications (ICCEA 2004), Beijing, China, 1-4 November, pp. 569-572.
Abstract: We discuss the architecture and microarchitecture of a scalable, parametric vector accelerator for the TLM algorithm. Architecture-level experimentation demonstrates an order of magnitude complexity reduction for vector lengths of 16 32-bit single-precision elements. We envisage the proposed architecture replicated in a SOC environment thus, forming a multiprocessor system capable of tapping parallelism at the thread level as well as the data level.
Description: This is a conference paper [© IEEE]. It is also available from: http://ieeexplore.ieee.org/. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Version: Published
DOI: 10.1109/ICCEA.2004.1459419
URI: https://dspace.lboro.ac.uk/2134/6168
ISBN: 0780385624
Appears in Collections:Conference Papers and Contributions (Electronic, Electrical and Systems Engineering)

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