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|Title: ||Techniques for algorithm design on the instruction systolic array|
|Authors: ||Schmidt, Bertil|
|Keywords: ||Parallel computing|
Instruction Systolic Array
|Issue Date: ||1999|
|Publisher: ||© Bertil Schmidt|
|Abstract: ||Instruction systolic arrays (ISAs) provide a programmable high performance hardware for
specific computationally intensive applications. Typically, such an array is connected to a
sequential host, thus operating like a coprocessor which solves only the computationally
intensive tasks within a global application. The ISA model is a mesh connected processor
grid, which combines the advantages of special purpose systolic arrays with the flexible
programmability of general purpose machines.
The subject of this thesis is the analysis, design, and implementation of several special
purpose algorithms and subroutines on the ISA that take advantage of the special features of
the systolic information flow.
The ability of ISAs to perform parallel prefix computations in an extremely efficient way is
exploited as a key-operation to derive efficiency as well as local operations within each
processor. Therefore, given sequential algorithms has to be decomposed in simple building
blocks of parallel prefix computations and parallel local operations. To modify sequential
algorithms for a parallelisation several techniques are introduced in this thesis, e. g. swapping
of loops in the sequential algorithm, shearing of data, and appropriate mapping of input data
onto the processor array
It is demonstrated how these techniques can be exploited to derive efficient ISA algorithms
for several computationally intensive applications. These include cryptographic applications
(e. g. arithmetic operations on long operands, RSA encryption, RSA key generation) and image
processing applications (e. g. convolution, Wavelet Transform, morphological operators,
median filter, Fourier Transform, Hough Transform, Morphological Hough Transform, and
tomographic image reconstruction).
Their implementation on Systola 1024 - the first commercial parallel computer with the ISA
architecture - shows that the concept of the ISA is very suitable for these applications and
results in significant run time savings.
The results of this thesis emphases the suitability of the ISA concept as an accelerator for
computationally intensive applications in the areas of cryptography and image processing.
This might lead research towards further high-speed low cost systems based on ISA hardware.|
|Description: ||A Doctoral Thesis. Submitted in partial fulfillment of the requirements for the award of Doctor of Philosophy of Loughborough University.|
|Appears in Collections:||PhD Theses (Computer Science)|
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